FPU synthesis error within the `lzc` module

Good afternoon!

I am trying to synthesize the CVW's FPU block (only single block without other parts of the CPU) and getting wierd error by Quartus Prime synthesis.

The error states the following:

It appears on the line 36 of the lzc.sv file. The module instantiated in the parent module fmalza.sv line 59.

After updating while loop with stricter stop condition everything starts to work. The update looks like the following: while ((i < WIDTH-1) & ~num[WIDTH-1-i]) i = i+1; // search for leading one

I am not sure about exact reasons causing the error and the correctness of my solution. I was concerned about the error and decided to report it here just in case.

Quartus Prime version: Lite 21.1.1