Not Getting Full coverage for Zalrsc_sc_w with trace-coverreport.py
Zarlsc_sc_w gets full coverage when run on wally, but misses cp_custom_sc_addresses (cp_address_difference: bins 14 and 15) when collecting coverage from the sail log.
RUnning on wally with 100%:
- wsim rv32gc WALLY-COV-Zalrsc-sc.w.S --lockstepverbose>log
- make merge
Running sail:
- make cvw-riscv-arch-test
summary_rv32i.txt: TYPE Zalrsc_sc_w_cg 99.06% 100 uncovered_rv32i.txt:
TYPE /RISCV_coverage_pkg/RISCV_coverage__1/Zalrsc_sc_w_cg
99.06% 100 - Uncovered
covered/total bins: 285 288 -
missing/total bins: 3 288 -
% Hit: 98.95% 100 -
Coverpoint cp_address_difference 93.75% 100 - Uncovered
covered/total bins: 15 16 -
missing/total bins: 1 16 -
% Hit: 93.75% 100 -
bin auto[0] 20 1 - Covered
bin auto[1] 1 1 - Covered
bin auto[2] 1 1 - Covered
bin auto[3] 2 1 - Covered
bin auto[4] 2 1 - Covered
bin auto[5] 1 1 - Covered
bin auto[6] 2 1 - Covered
bin auto[7] 2 1 - Covered
bin auto[8] 1 1 - Covered
bin auto[9] 2 1 - Covered
bin auto[10] 2 1 - Covered
bin auto[11] 1 1 - Covered
bin auto[12] 2 1 - Covered
bin auto[13] 2 1 - Covered
bin auto[14] 0 1 - ZERO
bin auto[15] 1 1 - Covered
Cross cp_custom_sc_addresses 87.50% 100 - Uncovered
covered/total bins: 14 16 -
missing/total bins: 2 16 -
% Hit: 87.50% 100 -
Auto, Default and User Defined Bins:
bin <lr_w,auto[13]> 1 1 - Covered
bin <lr_w,auto[12]> 1 1 - Covered
bin <lr_w,auto[11]> 1 1 - Covered
bin <lr_w,auto[10]> 1 1 - Covered
bin <lr_w,auto[9]> 1 1 - Covered
bin <lr_w,auto[8]> 1 1 - Covered
bin <lr_w,auto[7]> 1 1 - Covered
bin <lr_w,auto[6]> 1 1 - Covered
bin <lr_w,auto[5]> 1 1 - Covered
bin <lr_w,auto[4]> 1 1 - Covered
bin <lr_w,auto[3]> 1 1 - Covered
bin <lr_w,auto[2]> 1 1 - Covered
bin <lr_w,auto[1]> 1 1 - Covered
bin <lr_w,auto[0]> 3 1 - Covered
bin <*,auto[15]> 0 1 1 ZERO
bin <*,auto[14]> 0 1 1 ZERO Values obtained when running the wsim on wally for this coverpoint:
# sc.w: rs1=2147508312, prev_rs1=2147508224, diff[6:3]=11, lr.w,lr.d=10
# sc.w: rs1=2147508320, prev_rs1=2147508224, diff[6:3]=12, lr.w,lr.d=10
# sc.w: rs1=2147508328, prev_rs1=2147508224, diff[6:3]=13, lr.w,lr.d=10
# sc.w: rs1=2147508336, prev_rs1=2147508224, diff[6:3]=14, lr.w,lr.d=10
# sc.w: rs1=2147508344, prev_rs1=2147508224, diff[6:3]=15, lr.w,lr.d=10