Invalid Type Assignment in uvma_rvfi_instr_seq_item.sv

In lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv we see this: mode = rvfi.mode;, where mode is an enum of type uvma_rvfi_mode (defined in lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv) and rvfi.mode is of type logic [MAX_LEN-1:0] (defined in lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv).

I believe that this is an illegal assignment. It seems that VCS accepts this code, but DSim report an InvalidTypeAssign error at compile time. @ASintzoff I am assigning this issue to you because I know you have access to VCS and that the CVA6 uses this code. Do you also have access to another simulator to see if it complains about this code? In the meantime, I am thinking about a workaround...