[fail]Front-end error reported: RuntimeError: Error code: 4

Hi,

If I change the vector length to 256 and element length to 32 in the config/riscv_rv32.config and fpix/config/riscv_rv32.config and run $FORCE_PATH/utils/regression/master_run.py -f $FORCE_PATH/tests/riscv/_rv32_fctrl.py -c $FORCE_PATH/utils/regression/config/_riscv_rv32_fcfg.py -k all

Changes:

diff --git a/config/riscv_rv32.config b/config/riscv_rv32.config
index 04de69f..51740af 100644
--- a/config/riscv_rv32.config
+++ b/config/riscv_rv32.config
@@ -25,8 +25,8 @@
-    <limit name="MaxPhysicalVectorLen" value = "512"/>
-    <limit name="MaxVectorElementWidth" value = "64"/>
+    <limit name="MaxPhysicalVectorLen" value = "256"/>
+    <limit name="MaxVectorElementWidth" value = "32"/>
diff --git a/fpix/config/riscv_rv32.config b/fpix/config/riscv_rv32.config
index 6aba443..1e7dc91 100644
--- a/fpix/config/riscv_rv32.config
+++ b/fpix/config/riscv_rv32.config
@@ -23,8 +23,8 @@
-    <option name="vlen" default_value="512" description="vector register length in bits"/>
-    <option name="elen" default_value="64" description="maximum vector element width in bits"/>
+    <option name="vlen" default_value="256" description="vector register length in bits"/>
+    <option name="elen" default_value="32" description="maximum vector element width in bits"/>

I am getting following results:

Generate    : 136
Generate Fails:  27
Generate Success Rate : 80.15%

ISS Sim   : 107
ISS Sim Fails:   0
ISS Sim Success Rate : 100.00%

Total Instructions Emulated: 59502

Total Tasks     : 136
Task Fails      :  27
Task Success Rate: 80.15%

Total Run Time: 9.95404 Seconds

####
#### Reached max fails limit before test was completed.
####
Test Completed ....

All the 27 generate fails are pointing similar failure signature, example error message as follow:

[fail]Front-end error reported: RuntimeError: Error code: 4, Problems writing simulator register. CPU ID: 0, register: 'v28_4', value: 0x4c099e6aa4c17f0d, mask: 0xffffffffffffffff

  File "/data/shared/mulberry/users/udchetan/force-riscv-7-18/force-riscv/py/base/GenThreadExecutor.py", line 62, in executeGenThread
    aGenThread.generate()
  File "/data/shared/mulberry/users/udchetan/force-riscv-7-18/force-riscv/py/base/GenThread.py", line 151, in generate
    seq.run()
  File "/data/shared/mulberry/users/udchetan/force-riscv-7-18/force-riscv/py/base/Sequence.py", line 49, in run
    self.generate(**kargs)
  File "/data/shared/hcg/users/udchetan/force-riscv-7-18/force-riscv/tests/riscv/instructions/v_instructions/T10-Group4_force.py", line 19, in generate
    self.genInstruction(instr, {"NoSkip":1})
  File "/data/shared/mulberry/users/udchetan/force-riscv-7-18/force-riscv/py/base/Sequence.py", line 97, in genInstruction
    return self.genThread.genInstruction(instr_name, kargs)
  File "/data/shared/mulberry/users/udchetan/force-riscv-7-18/force-riscv/py/base/GenThread.py", line 181, in genInstruction
    return self.interface.genInstruction(self.genThreadID, instr_name, kargs)

[FAIL]{front-end-error-reported} in file '../base/inc/py_modules/PyLog.h' line 58 func 'operator()'.

Has anyone faced the similar issue? Am I missing any configuration settings here? Any thoughts/comments would be highly appreciated. Thanks.