"Prime 32-bit SIMD/FP registers" choice missing from "operand choices" in arch data

Hello,

In the rv32 instructions file: https://github.com/openhwgroup/force-riscv/blob/master/riscv/arch_data/instr/c_instructions_rv32.xml , the "C.FSW" instruction has choices="Prime 32-bit SIMD/FP registers". However, this choice "Prime 32-bit SIMD/FP registers" is not found in the operand choices file (https://github.com/openhwgroup/force-riscv/blob/master/riscv/arch_data/general/operand_choices.xml). However, other choices such as "Prime 64-bit SIMD/FP registers" and "32-bit SIMD/FP registers" are valid choices in the file.

Is this an oversight, or an intended feature?