Bit width discrepancy in multiply-accumulate documentation

Created by: DavidM-EMUS

In the documentation at the below link: https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/instruction_set_extensions.html#multiply-accumulate

In section Pulp Instruction Set Extensions > Multiply-Accumulate, bit width for instructions that utilise the upper half of the input registers have the bit range used as [31:15], when they should state that the range is [31:16]. For example, for instruction p.muls, the description of its functionality reads as such: rD[31:0] = Sext(rs1[15:0]) * Sext(rs2[15:0])

while instruction p.mulhhs, (its upper-half utilising counterpart) reads as such: rD[31:0] = Sext(rs1[31:15]) * Sext(rs2[31:15])

This is faulty information for p.mulhhs, as testing with the rtl shows that the bit range used is [31:16]. This affects descriptions of 10 instructions in total: p.mulhhs, p.mulhhsN, p.mulhhsRN, p.mulhhu, p.mulhhuN, p.mulhhuRN, p.machhsN, p.machhsRN, p.machhuN, and p.machhuRN