Cycle counts for multiply and divide not correct in documentation

Created by: Silabs-ArjanB

The documentation (multiply_accumulate.rst) states the following:

The multiplications with upper-word result (MSP of 32-bit x 32-bit multiplication), take 4 cycles to compute. The division and remainder instructions take between 2 and 32 cycles. The number of cycles depends on the operand values.

The above is not correct for mulh*, div* and rem* instructions.

• mul instructions take 1 cycle (based on the RTL FSM)
• mulh, mulhsu, mulhu take 5 cycles (based on the RTL FSM)

For div, divu, rem, remu instructions I am not sure what the range is, but for sure these instructions can take 31, 32, 34, 35 cycles (counts based on simulation, not on RTL code analysis).

So remaining question is: What is the cycle count range for div, divu, rem, remu instructions and is it easy to explain the rules depending on the operand values?

The multiply_accumulate.rst file will be removed, so please don't update that file, but answer the question in this ticket (I am adding a cycle count table in pipeline.rst).