Which Instruction Fetch does CV32E40P and CV32E40 use?

Section 2 of the RI5CY user manual states:

There are two prefetch flavors available:
* 32-Bit word prefetcher. It stores the fetched words in a FIFO with three entries.
* 128-Bit cache line prefetcher. It stores one 128-bit wide cache line plus 32-bit to allow for cross-cache line misaligned instructions.

Several questions arise:

1. Are these mutually exclusive logic modules? If so:

• How are they selected at simulation compile-time and synthesis time?
• Which of these are being used by CV32E40P and CV32E40?

2. If these are not mutually exclusive, how does the prefetch unit logic determine which will be used to prefetch from the cache and why?