Purpose of use of scan_cg_en_i not clear

The User Manual makes two references to primary input scan_cg_en_i:

• The Interfaces table in core integration states: "Scan clock gate enable".
• In the Getting Starting section the UM references scan_cg_en_i in the clock gating cell sub-section, but goes not explicitly state what the use should to with the input.

Neither of these references makes it clear to the user of the core what should be done with this input. I recommend that Core Integration chapter have an explicit recommendation for driving this input.

It is my understanding that setting scan_cg_en_i forces the clock to the register file to be always enabled, but if scan_cg_en_i is de-asserted then the WB stage will enable reg-file clock as needed. Is that correct?

Note that the verification environment has scan_cg_en_i hardwired to 1'b0.