Incorrect operands for pv.(extract/extractu/insert).(h/b)

Created by: DavidM-EMUS

In the SIMD ALU Encoding section of the documentation at https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/instruction_set_extensions.html#simd-alu-encoding instructions pv.extract.h, pv.extract.b, pv.extractu.h, pv.extractu.b, pv.insert.h, and pv.insert.b all have their operands listed as "rD, Imm6" This conflicts with the description and performance of the instructions, in which all require a register, rs1, as well. This can be seen in the description of pv.extract.h: rD = Sext(rs1[((I+1)*16)-1 : I*16]) where I is a stand-in for Imm6. Changing the operands from "rD, Imm6" to "rD, rs1, Imm6" in the SIMD ALU Encoding section for the instructions listed above should remedy this issue.