CV32E40P User Manual: specification of uhartid CSR

Type

Issues with this CSR as documented:

• uhartid is not part of the RISC-V ISA so it needs to be in a "custom" address space.
• mhartid is part of the RISC-V ISA and it is supported by CV32E40P. How is this CSR different than that one?
• The CSR is located at 0x14, which is "standard read-only" space.
• The description of the CSR is incomplete (I can't tell what it does from the description).

Location of Issue

1. RTD URL: https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/control_status_registers.html?highlight=privlv#user-hardware-thread-id-uhartid
2. core-v-docs Git Hash: 609007a1