Vplan: timing of debug_req_i pulse

Bug Title

Update Debug Vplan to consider timing of debug_req_i assertion and de-assertion.

Type

Potentially missing information in the Vplan

Decription of Issue

CV32E40P issue #404 highlights an issue with the timing of the assertion of debug_req_i. To the best of my knowledge, we have no features captured in the Debug Vplan that would cause us to exercise and catch this and related cycle timing issues. Please review the CV32E40P issue and make appropriate updates to the Debug Vplan.

Additional context

Please discuss with @Silabs-ArjanB to see if there is a potential for similar issues.
If there are similar issues related to features other than Debug, please bring them to my attention.