posting for - OpenHW TV S03/E08 – Advancing RISC-V Processor Verification
Created by: michelleclancy
Here is the next episode for posting under OpenHW TV - please also post on under the news section when it is posted. thank you,
OpenHW TV S03/E08 – Advancing RISC-V Processor Verification
Abstract:
This OpenHW TV episode introduces the new Chair of the OpenHW Verification Task Group and the expanded charter to help support the growing RISC-V Verification Ecosystem.
The OpenHW Group welcomes Simon Davidmann of Imperas Software, a founding member of OpenHW, as the new Chair of the OpenHW Verification Task Group (VTG). As part of the CORE-V roadmap, the VTG is updating the successful CORE-VERIF framework to address both the increasing design complexity and improve the DV efficiency for the anticipated bandwidth required for all the new CORE-V cores in development.
To address the dual goals of improving and enhancing the OpenHW internal flows for the CORE-V roadmap and help lead the industry adoption of RISC-V, and the associated verification workload, the VTG has started a new methodology project. This episode highlights the new OpenHW VTG Advanced RISC-V Verification Methodology (ARVM) project and outlines the initial concepts and plans for a couple of the sub-projects:
• ARVM-FunctionalCoverage: developing open-source VIPs that can be used for many different core configurations/implementations
• ARVM-Standards: defining and implementing evolving interface standards (such as RVVI) for test bench components to enable better test bench component reuse and potentially stimulate availability of compatible VIPs
Today's speakers include:
• Simon Davidmann, Chair of OpenHW Verification Task Group and CEO at Imperas Software
• Peter Lewin, Director of CPU Ecosystems at Imagination Technologies
• Rupert Baines, Chief Marketing Officer at Codasip
• Hosted by Mike Thompson, Director of Engineering, Verification Task Group, at OpenHW Group
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