bug may exist in page-fault exception handler

Created by: niuqiang-real

Hi there,

I'm currently using FORCE to generate some load/store instructions without preamble instructions. Lots of my generation failed for one same reason. After some debugging, I believe these fails were caused by a bug in FORCE. And I would be grateful if you can help me to confirm it.

In the official description about Sv48, there is a description about one of there exceptions: Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–48 all equal to bit 47, or else a page-fault exception will occur.

Comprehensive page fault exception handler uses an OS like approach to service many page related exceptions. It checks the faulting address, tries to correct it when it's illegal, writes the modified address into XTVAL and returns.

BUT this is not enough. After returning from exception subroutine, PC points to the same instruction that caused this page fault exception. Executing it will raise the same exception again. Core will repeat this process until exceed instruction upper-limit and generation fails.

Thanks!