Misaligned Faults concurrent with TLB miss

Created by: rosethompson

Misaligned faults may be asserted when a TLB miss occurs. Because Wally only implements misaligned support for cacheable memory, the address must be translated before cacheablity is known. Table 15 of the privileged spec defines the priority of faults and Wally places misaligned after page faults. of We need to create a test case and update the HPTW to suppress these faults during a TLB miss.