Verilator incorrectly simulates some regression suites

Created by: davidharrishmc

running regression-wally with Verilator as the defaultsim fails on 24 test suites, mostly on floating-point suites with large signatures. These tests pass in Questa. The f tests mostly fail at result 1020 and d at 510, which suggests a memory size issue.

harris@chips:~/cvw/sim/verilator$ wsim -s verilator rv32gc arch32f
Config=rv32gc tests=arch32f sim=verilator gui=False args=''
Running Verilator on rv32gc arch32f
make: Entering directory '/home/harris/cvw/sim/verilator'
mkdir -p /home/harris/cvw/sim/verilator/logs
wkdir/rv32gc_arch32f/Vtestbench +TEST=arch32f
%Warning: System has stack size 100000 kb which may be too small; suggest 'ulimit -c 156273' or larger
  Error on test rv32i_m/F/src/fadd_b11-01.S result        1020: adr = 8007c100 sim (D$) deadbeef signature = 00000000
%Error: /home/harris/cvw/testbench/testbench.sv:879: Verilog $stop

The bad sw to 8007c100 occurs at time 163,010 in both Questa and Verilator. The value DEADBEEFDEADBEEFDEADBEEF00000000 should be written to the cache way 2 word 0 address 4. Both Questa and Verilator show this happening.

DCacheFlushStart is asserted at 3,006,250 in Questa but not in Verilator.

PCM is 80023EA4 at time 999999 in Verilator but at 999355 in Questa. PCM is 80012074 at time 499999 in V but 505290 in Q 80003468 at time 99,999 in both 200k Questa and Verilator in sync V at 80012068 at 499825, Q at 505260 300k sync 400k out of sync 349924 out of sync (maybe ok) 320k in sync 330k in sync 339,887 in sync keep searching later