Instruction page fault raised incorrectly
Created by: eroom1966
Hi @ross144
I am running more of the riscv-dv tests, it looks like we have an issue with an 'Instruction Page Fault' raised, and we do not think it should be.
I am attaching the elf file as before.
The symptom is with the fetch of instruction at (virtual) address 0x74fc It appears that the test repeatedly flushes the TLB entries using an sfence.vma, pages get remapped but at instruction 23648 we have the fault occurring in the RTL
I am not sure of the size of the TLB in the RTL but the last sequence we observe is a TLB ENTRY creation for VA 0x7000 - 0x7FFF we see a number of instructions execute, then instruction at address 0x74fc takes the 'Instruction Page Fault'
below you can see that the RTL takes the fault handler whereas the REF execute the instruction which the RTL reported as the faulting address
# [NOTE] testbench.idv_trace2log @ 1156711: RET,0,23647,000074f8,"0000100f fence.i ",,,,CSRb00(mcycle)=000000000001c3d2 CSRb02(minstret)=0000000000005c5f,
# Info 23647: 'refRoot/cpu', 0x00000000000074f8(sub_3_86_0_t+3a): Supervisor 0000100f fence.i
# Info MEMX 0x74f8 0x800074f8 2 100f
# Info MEMX 0x74fa 0x800074fa 2 0000
# [NOTE] testbench.idv_trace2log @ 1157001: RET,0,23648,8000f000,"1df1 c.addi x27,x27,-4 ",x27=000000008003fcf4,,,CSR300(mstatus)=0000000a00040800 CSR341(mepc)=00000000000074fc CSR342(mcause)=000000000000000c CSR343(mtval)=00000000000074fc CSRb00(mcycle)=000000000001c3ef CSRb02(minstret)=0000000000005c60,
# Info 23648: 'refRoot/cpu', 0x00000000000074fc(sub_3_70_1_t): Supervisor 987d c.andi x8,x8,-1
# Info MEMX 0x74fc 0x800074fc 2 987d
# Error (IDV) PC mismatch (HartId:0, PC:0x00000000000074fc ):
# Info (IDV) 0>
# Info (IDV) . dut:0x000000008000f000
# Info (IDV) . ref:0x00000000000074fc
# Error (IDV) Insn. bit pattern mismatch (HartId:0, PC:0x00000000000074fc ):
# Info (IDV) 1>
# Info (IDV) . dut:1df1 c.addi x27,x27,-4
# Info (IDV) . ref:987d c.andi x8,x8,-1Thx Lee