fence.i does not appear to allow flushing of store before fetch

Created by: eroom1966

The following test riscv-arch-test/rv64i_m/Zifencei/src/Fencei.S

Performs a store to an address, prior to a fetch from the same address, using a fence.i to ensure it has flushed The RTL appears to read back the value prior to the store to instruction memory

x21 holds the address of the instruction x15 hold the instruction bit pattern (001101b3)

RTL fetches the stale bit pattern from memory (00000137) not the value stored prior to the fence.i

# [NOTE] testbench.idv_trace2log @ 4171: RET,0,239,800003b8,"014a8a93 addi    x21,x21,20     ",x21=00000000800003c8,,,CSRb00(mcycle)=000000000000019c CSRb02(minstret)=00000000000000ef,
# Info 239: 'refRoot/cpu', 0x00000000800003b8(rvtest_code_begin+28): Machine 014a8a93 addi    x21,x21,20
# Info   x21 00000000800003b4 -> 00000000800003c8
# [NOTE] testbench.idv_trace2log @ 4181: RET,0,240,800003bc,"000a2783 lw      x15,0(x20)     ",x15=00000000001101b3,,,CSRb00(mcycle)=000000000000019d CSRb02(minstret)=00000000000000f0,
# Info 240: 'refRoot/cpu', 0x00000000800003bc(rvtest_code_begin+2c): Machine 000a2783 lw      x15,0(x20)
# Info   x15 fab7fbb6fab7fbb6 -> 00000000001101b3
# [NOTE] testbench.idv_trace2log @ 4291: RET,0,241,800003c0,"00faa023 sw      x15,0(x21)     ",,,,CSRb00(mcycle)=00000000000001a8 CSRb02(minstret)=00000000000000f1,
# Info 241: 'refRoot/cpu', 0x00000000800003c0(rvtest_code_begin+30): Machine 00faa023 sw      x15,0(x21)
# [NOTE] testbench.idv_trace2log @ 4301: RET,0,242,800003c4,"0000100f fence.i                ",,,,CSRb00(mcycle)=00000000000001a9 CSRb02(minstret)=00000000000000f2,
# Info 242: 'refRoot/cpu', 0x00000000800003c4(rvtest_code_begin+34): Machine 0000100f fence.i
# [NOTE] testbench.idv_trace2log @ 4431: RET,0,243,800003c8,"00000137 lui     x2,0x0         ",x2=0000000000000000,,,CSRb00(mcycle)=00000000000001b6,
# Info 243: 'refRoot/cpu', 0x00000000800003c8(instr_A_dst): Machine 001101b3 add     x3,x2,x1
# Info   x3 0000000000000000 -> 0000000000000042
# Error (IDV) Insn. bit pattern mismatch (HartId:0, PC:0x00000000800003c8 instr_A_dst+0):
# Info (IDV)  0>
# Info (IDV)   . dut:00000137 lui     x2,0x0
# Info (IDV)   . ref:001101b3 add     x3,x2,x1
# Error (IDV) GPR register value mismatch (HartId:0, PC:0x00000000800003c8 instr_A_dst+0):
# Info (IDV)  1> GPR x2
# Info (IDV)   . dut:0x0000000000000000 
# Info (IDV)   . ref:0x0000000000000012 
# Info (IDV)  2> GPR x3
# Info (IDV)   . dut:0x0000000000000000 
# Info (IDV)   . ref:0x0000000000000042