CSR register sie is not observing the mideleg register
Created by: eroom1966
If I run the Wally test WALLY-mtvec-01.S sie is updated with the same (masked contents) as mie, however this should also observe the value of the corresponding bits in mideleg
Section 3.1.9 of Privileged Specification: Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie are read-only zero
So if the mideleg bits are 0 (which they are in this case) then the corresponding sie bits should also be 0
elf file attached