Discrepancies between Wally and ImperasDV

Created by: davidharrishmc

As I interpret the spec, mseccfg should be optional in the latest spec. "mseccfg is an optional 64-bit read/write register" Wally traps if it is accessed. ImperasDV does not. Do you agree it should be optional and that Wally behavior should be legal? If so, is there a configuration option to get that behavior, or could Imperas add one?

Wally traps on accesses to 7a0-7af machine mode debug-related registers and by default ImperasDV does not. cpu/debug_mode=none made ImperasDV trap on 7b0-7bf, but not on 7a0-7af. These are tselect, tdata1, tdata2, tdata3, and mcontext. It looks like there is a mcontext_undefined flag but none for the other trace registers. Is there another switch I should use?