[BUG] When taking a synchronous exception, bit 6 (sync_exc_seen) should be set in the CPUCTRL CSR (0x7C0)

Created by: LeeHoff

Bug Description

With the updated reference model, running debug_test with USE_ISS=YES, the reference model sets bit 6 sync_exc_seen in the cpuctrl (0x7c0) register. This CSR is not implemented in the RTL, but it is in the CVE2 spec.