[DCache] Back to back Store instruction corrupt data cache
Created by: zarubaf
Here's the load/store instruction that access PA 'h800c6020 ~ 'h800c6027. The load data 00000000fffe0000 of the last instruction is incorrect.
217541500 217532 000000000001ceee 0 ffceb123 sd t3, -30(t4) t3 :0000000080000000 t4 :00000000000c603e VA: 00000000000c6020 PA: 00000000800c6020
517840500 517831 000000000004092e 0 ff05b683 ld a3, -16(a1) x13 =0000000080000000 a1 :00000000000c6030 VA: 00000000000c6020 PA: 00000000800c6020
735718500 735709 000000000005adb8 0 e436c683 lbu a3, -445(a3) x13 =0000000000000000 a3 :00000000000c61e1 VA: 00000000000c6024 PA: 00000000800c6024
884744500 884735 000000000006c5e0 0 00f5e503 lwu a0, 15(a1) x10 =00000000fffe0000 a1 :00000000000c6015 VA: 00000000000c6024 PA: 00000000800c6024Mismatch:
ERROR: Mismatch: Instr[105239] Spike reg[10] = 0000000000000000 RTL reg[10] = 00000000fffe0000
Spike instruction : lwu a0, 15(a1)
RTL sim instruction : lwu a0, 15(a1)
ERROR: Mismatch: Instr[105856] Spike reg[22] = 000000000000fffe RTL reg[22] = 0000000000000000
Spike instruction : lhu s6, -106(a3)
RTL sim instruction : lhu s6, -106(a3)
ERROR: Mismatch: Instr[162156] Spike reg[13] = 00000000fffe0000 RTL reg[13] = 0000000000000000
Spike instruction : lwu a3, -369(s6)
RTL sim instruction : lwu a3, -369(s6)
ERROR: Mismatch: Instr[162161] Spike reg[22] = ffffffffffffffff RTL reg[22] = 0000000000000000
Spike instruction : mulh s6, a3, t3
RTL sim instruction : mulh s6, a3, t3 Looks like these two back-to-back store messed up the cache.
711994500 711985 0000000000057fec 0 eabebea3 sd a1, -323(t4) a1 :ffffffffff282001 t4 :00000000000c616b VA: 00000000000c6028 PA: 00000000800c6028
712003500 711994 0000000000058002 0 f8d51723 sh a3, -114(a0) a3 :fffffffffffffffe a0 :00000000000d0098 VA: 00000000000d0026 PA: 00000000800d0026