No response from interconnect when adding master

Created by: DvdBerg

Hello,

For the sake of achieving Direct Memory Access, I have created a small test module that reads a single memory address (0xBC000000) every 100 ms. This module is connected as master on the interconnect in the same way that the Ariane core is connected (using a req_t and resp_t connected to an axi_master_connect).

When trying to read a DRAM address, a response never arrives (r_valid never becomes high). I assumed the problem was in my test module, but when I change the address to one inside the bootrom instead of the DRAM, the response arrives correctly. To further inspect the issue, I have added debug probes to the AXI signals of both my own module and the DRAM. This results in the following waveforms:

Request in the test module:

Request to the DRAM:

Response from the DRAM:

So the request arrives correctly at the DRAM, and the response is correctly returned to the interconnect. However, this result never propagates back to the test module.