Avoid using System Verilog defines in RTL code

Created by: Silabs-ArjanB

The CVA6 uses the following defines (used in ifdef/ifndef statements):

• DROMAJO
• FIRESIM_TRACE
• FORMAL
• INSTR_TRACER_IF_SV
• PITON_ARIANE
• SYNTHESIS
• VERILATOR
• WT_DCACHE

Similar to the request made in https://github.com/openhwgroup/cv32e40p/issues/301 all such System Verilog defines should (ideally) be completely avoided in RTL code (and for example be replaced by localparam or parameter, avoided by a cleaner split between RTL and non-RTL code (in separate files), etc.). On CV32E40P all defines were avoided by rewrites performed in https://github.com/openhwgroup/cv32e40p/pull/389 (actually the define related to assertions is still there, but will soon be removed as well as assertions will move into seperate files outside of the RTL files). If for some reason defines will still be used, it would be cleaner if they use a uniform prefix (e.g. CVA6_) to reduce the chance of conflicts with other RTL code.