Wrong exception tval for instruction fetch fault if instruction is crossing page boundary

Created by: xushengj

When there is an instruction fetch causing page fault, according to riscv privileged instruction set document, mtval/stval "will ontain the virtual address of the portion of the instruction that caused the fault", but it seems that in the current implementation the PC is stored in the tval field. This causes hang when running some programs having a 32 bits instruction split across two pages; the fault appears to be in the first page while it should be on the second page.

The attachment is our current crafted binary that can trigger this hang in verilator and fpga running Linux, but successfully complete in QEMU. Test8.zip

For now we can work around this issue by disabling c extension during compilation of user level programs, which force all instructions to be 4 bytes aligned. We will try to make a PR for this issue.