Empty match file in FPGA flow

Created by: jimmysitu

Hi, All Code https://github.com/pulp-platform/ariane/blob/f66b2f19377b3c69409d53f85bb938e187dde411/fpga/scripts/run.tcl#L42 which cause empty match in FPGA flow

WARNING:` [Vivado 12-818] No files matched '*../src/common_cells/include/common_cells/registers.svh'
# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
# set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
# update_compile_order -fileset sources_1

I think this is a little better

 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*/$registers"]]