[BUG] : mcounteren does not raise an illegal exception

Created by: AyoubJalali

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Hello, in the risc-v specification dedicated for cv32a65x, the mcounteren CSR does not exist because there's no USER mode supported, but RTL threat it as a RO CSR, so it allows to read from it, and raise exception if we try to write into it.

But normally it should raise an exception on the read & write, here's a RTL log :