[BUG] AXI bus trouble with write-back cache

Created by: nlthales

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Hi, I got a SoC project using CVA6 cores, which is running well with its default configuration - cache in write-through mode (config_pkg::WT). I gave a try in write-back mode but without any success. Looking at the AXI bus, I can see some difference while doing the first write access, in an uncachable memory area. Discrepencies are shown hereafter: The AXI subsystem acknowledges the access in both situations, but in WB the access seems lost and does not result in an actual access to the target peripheral.