Previous privilege mode mstatus field MPP holds reserved value

Created by: salaheddinhetalani

Is there an existing CVA6 bug for this?

I have searched the existing bug issues

Bug Description

Previous privilege mode field, MPP, of mstatus or sstatus holds reserved value. The example where this applies to sstatus is not shown here.

RISC-V Specification

Unprivileged ISA: 20191213 | Privileged Architecture: 20211203 | External Debug Support: 0.13.02

Example Scenario

As shown below, the following sequence of instructions happens:

CSRRW x2, mstatus, x9 -> CSRRCI x1, mstatus, 0

The instruction CSRRW x2, mstatus, x9 is decoded at t_id and executed in machine mode resulting in updating the architecture state at t_arch_update. As a result, a wrong value of the MPP field of mstatus is read considering that it's a reserved one.

Steps to Reproduce

Git Hash: de2e254c | TARGET_CFG: cv32a6_imac_sv0 | VCD: issue_12.zip

Component

Component:RTL

Product: Questa OneSpin Solutions App: Questa Processor App Tool's version: 2024.1_1