[TASK] Cadence simulator support

Created by: CoralieAllioux

Is there an existing CVA6 task for this?

• I have searched the existing task issues

Task Description

Support additional simulator: Cadence xcelium. The support concerns uvm and testharness. It needs to be transparent for VCS users and adapt to the current flow.

Required Changes

Two new DV_SIMULATOR options to be add: xrun-uvm and xrun-testharness. It implies:

• UVM/RTL fixes in cva6 and core-v-verif
• Adapt cva6/verif/sim/Makefile
• Adapt cva6/verif/sim/cva6.yaml
• Adapt cva6/verif/sim/cva6-simulator.yaml
• Adapt cva6/verif/env/corev-dv/simulator.yaml

Probably additional files would be impacted and could be forgotten.

Current Status

In progress xrun-uvm almost done with riscv-dv support

Risks

Fixes to run a new simulator might not be straight forward and challenge the current file hierarchy or methodology.

Prerequisites

No response

KPI (KEY Performance Indicators)

No response

Description of Done

Complete vcs flow supported by Cadence Xcelium, while using DV_SIMULATOR xrun-uvm and xrun-testharness.

Associated PRs

No response