[BUG] `zext.h_64-01` verilator simulation failed
Created by: Siris-Li
Is there an existing CVA6 bug for this?
-
I have searched the existing bug issues
Bug Description
I can pass smoke test by running bash verif/regress/smoke-tests.sh
However, when I try to run bash verif/regress/dv-riscv-arch-test.sh, it will terminate when testing zext.h_64-01, here is the output log:
Makefile:14: must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...
make -C /home/sirisli/cva6/ verilate verilator="verilator --no-timing" target=cv64a6_imafdc_sv39 defines=
make[1]: Entering directory '/home/sirisli/cva6'
Makefile:143: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
[Verilator] Building Model
....
cd work-ver && make -j24 -f Variane_testharness.mk
make[2]: Entering directory '/home/sirisli/cva6/work-ver'
make[2]: Nothing to be done for 'default'.
make[2]: Leaving directory '/home/sirisli/cva6/work-ver'
make[1]: Leaving directory '/home/sirisli/cva6'
/home/sirisli/cva6//work-ver/Variane_testharness /home/sirisli/cva6/verif/sim/out_2024-01-12/directed_asm_tests/zext.h_64-01.o +debug_disable=1 +ntb_random_seed=1 \
+elf_file=/home/sirisli/cva6/verif/sim/out_2024-01-12/directed_asm_tests/zext.h_64-01.o +tohost_addr=0000000080002000
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 39375
/home/sirisli/cva6/verif/sim/out_2024-01-12/directed_asm_tests/zext.h_64-01.o *** FAILED *** (tohost = 2147483647) after 2000012 cycles
CPU time used: 31653.16 ms
Wall clock time passed: 31649.59 ms
make: *** [Makefile:141: veri-testharness] Error 255Edit:
I have tired other cases in dv-riscv-arch-test.sh, they all passed, that is, only zext.h_64-01 failed.
I notice only when running zext.h_64-01 case, verilator will raise these warnings:
Verilator Warnings
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/cva6.sv:166:66: Logical operator LOGAND expects 1 bit on the LHS, but LHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6'
166 | localparam bit NonIdemPotenceEn = CVA6Cfg.NrNonIdempotentRules && CVA6Cfg.NonIdempotentLength;
| ^~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.018
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/cva6.sv:166:66: Logical operator LOGAND expects 1 bit on the RHS, but RHS's SEL generates 1024 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6'
166 | localparam bit NonIdemPotenceEn = CVA6Cfg.NrNonIdempotentRules && CVA6Cfg.NonIdempotentLength;
| ^~
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/include/wt_cache_pkg.sv:286:18: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim'
286 | 2'b00: be[offset] = '1;
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/include/wt_cache_pkg.sv:287:18: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim'
287 | 2'b01: be[offset+:2] = '1;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/include/wt_cache_pkg.sv:290:5: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'be' generates 4 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim'
290 | return be;
| ^~~~~~
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/mmu_sv39/mmu.sv:260:41: Operator ASSIGN expects 129 bits on the Assign RHS, but Assign RHS's REPLICATE generates 137 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu'
260 | icache_areq_o.fetch_exception = {
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/cache_subsystem/wt_axi_adapter.sv:156:19: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's REPLICATE generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter'
156 | axi_wr_user = {{64 - CVA6Cfg.AxiUserWidth{1'b0}}, dcache_data.user};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/cache_subsystem/wt_axi_adapter.sv:158:19: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's REPLICATE generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter'
158 | axi_wr_user = {dcache_data.user, {64 - CVA6Cfg.AxiUserWidth{1'b0}}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/cache_subsystem/wt_axi_adapter.sv:268:33: Operator NOT expects 128 bits on the LHS, but LHS's REPLICATE generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter'
268 | axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / riscv::XLEN) {dcache_data.user}};
| ^
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:218:39: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
218 | assign miss_wdata[k] = {{riscv::XLEN} {1'b0}};
| ^~~~
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:218:31: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
218 | assign miss_wdata[k] = {{riscv::XLEN} {1'b0}};
| ^
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:219:31: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
219 | assign miss_wuser[k] = {{DCACHE_USER_WIDTH} {1'b0}};
| ^
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:220:36: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
220 | assign miss_vld_bits_o[k] = {{DCACHE_SET_ASSOC} {1'b0}};
| ^
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:221:39: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
221 | assign miss_paddr[k] = {{riscv::PLEN} {1'b0}};
| ^~~~
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:221:31: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
221 | assign miss_paddr[k] = {{riscv::PLEN} {1'b0}};
| ^
%Warning-WIDTHCONCAT: /home/sirisli/cva6/core/cache_subsystem/wt_dcache.sv:224:28: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_cache_wt.i_cache_subsystem.i_wt_dcache'
224 | assign miss_id[k] = {{CACHE_ID_WIDTH} {1'b0}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/cvxif_fu.sv:93:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'illegal_instr_n' generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.gen_cvxif.cvxif_fu_i'
93 | x_exception_o.tval = illegal_instr_n;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/fpu_wrap.sv:406:39: Operator COND expects 64 bits on the Conditional False, but Conditional False's REPLICATE generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.fpu_gen.fpu_i'
406 | operand_c_d = CVA6Cfg.RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/fpu_wrap.sv:408:39: Operator COND expects 64 bits on the Conditional False, but Conditional False's REPLICATE generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.fpu_gen.fpu_i'
408 | operand_c_d = CVA6Cfg.RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/fpu_wrap.sv:415:39: Operator COND expects 64 bits on the Conditional False, but Conditional False's REPLICATE generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.fpu_gen.fpu_i'
415 | operand_b_d = CVA6Cfg.RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/fpu_wrap.sv:417:39: Operator COND expects 64 bits on the Conditional False, but Conditional False's REPLICATE generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.fpu_gen.fpu_i'
417 | operand_b_d = CVA6Cfg.RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}};
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/mult.sv:98:21: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.i_mult'
98 | operand_a = fu_data_i.operand_a[31:0];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/mult.sv:99:21: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.i_mult'
99 | operand_b = fu_data_i.operand_b[31:0];
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/mult.sv:137:57: Operator FUNCREF 'sext32' expects 32 bits on the Function Argument, but Function Argument's VARREF 'result' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.i_mult'
137 | assign div_result = (riscv::IS_XLEN64 && word_op_q) ? sext32(result) : result;
| ^~~~~~
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:81:78: Operator SHIFTL expects 64 bits on the LHS, but LHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
81 | SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
| ^~
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:82:78: Operator SHIFTL expects 64 bits on the LHS, but LHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
82 | SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
| ^~
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:83:78: Operator SHIFTL expects 64 bits on the LHS, but LHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
83 | SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
| ^~
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:84:50: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'operand_a_rev32' generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
84 | CTZW: operand_a_bitmanip = operand_a_rev32;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:85:50: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
85 | ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:287:52: Operator COND expects 64 bits on the Conditional False, but Conditional False's VARREF 'shift_result32' generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
287 | SLL, SRL, SRA: result_o = (riscv::IS_XLEN64) ? shift_result : shift_result32;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:297:167: Operator SUB expects 32 or 7 bits on the RHS, but RHS's SEL generates 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
297 | rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/alu.sv:297:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's OR generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
297 | rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:298:167: Operator SUB expects 32 or 7 bits on the RHS, but RHS's SEL generates 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
298 | rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/alu.sv:298:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's OR generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
298 | rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:336:250: Operator SUB expects 32 or 7 bits on the RHS, but RHS's SEL generates 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
336 | result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/alu.sv:339:250: Operator SUB expects 32 or 7 bits on the RHS, but RHS's SEL generates 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.alu_i'
339 | result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/scoreboard.sv:230:61: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'issue_en' generates 1 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.issue_stage_i.i_scoreboard'
230 | assign issue_pointer_n = (flush_i) ? '0 : issue_pointer_q + issue_en;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/scoreboard.sv:234:71: Operator ADD expects 32 bits on the LHS, but LHS's SEL generates 3 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.issue_stage_i.i_scoreboard'
234 | assign commit_pointer_n[k] = (flush_i) ? '0 : commit_pointer_n[0] + unsigned'(k);
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/scoreboard.sv:234:32: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.issue_stage_i.i_scoreboard'
234 | assign commit_pointer_n[k] = (flush_i) ? '0 : commit_pointer_n[0] + unsigned'(k);
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/perf_counters.sv:157:39: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
157 | if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/perf_counters.sv:167:18: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
167 | data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/perf_counters.sv:176:14: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's ARRAYSEL generates 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
176 | data_o = mhpmevent_q[addr_i-riscv::CSR_MHPM_EVENT_3+1];
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/perf_counters.sv:190:73: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'data_i' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
190 | generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0] = data_i;
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/perf_counters.sv:200:75: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'data_i' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
200 | generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32] = data_i;
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/perf_counters.sv:209:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'data_i' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.gen_perf_counter.perf_counters_i'
209 | mhpmevent_d[addr_i-riscv::CSR_MHPM_EVENT_3+1] = data_i;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:185:46: Operator COND expects 64 bits on the Conditional False, but Conditional False's REPLICATE generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
185 | assign mstatus_extended = riscv::IS_XLEN64 ? mstatus_q[riscv::XLEN-1:0] :
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:307:44: Operator OR expects 64 bits on the RHS, but RHS's VARREF 'fiom_q' generates 1 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
307 | riscv::CSR_MENVCFG: csr_rdata = '0 | fiom_q;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:322:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
322 | if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:326:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
326 | if (riscv::XLEN == 32) csr_rdata = instret_q[63:32];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:330:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
330 | if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:334:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
334 | if (riscv::XLEN == 32) csr_rdata = instret_q[63:32];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:509:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
509 | if (riscv::XLEN == 32) csr_rdata = pmpcfg_q[7:4];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:513:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
513 | if (riscv::XLEN == 32) csr_rdata = pmpcfg_q[15:12];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:538:63: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's SEL generates 54 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
538 | if (pmpcfg_q[index].addr_mode[1] == 1'b1) csr_rdata = pmpaddr_q[index][riscv::PLEN-3:0];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:539:26: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's REPLICATE generates 54 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
539 | else csr_rdata = {pmpaddr_q[index][riscv::PLEN-3:1], 1'b0};
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/csr_regfile.sv:862:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'csr_wdata' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
862 | if (riscv::XLEN == 32) cycle_d[63:32] = csr_wdata;
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/csr_regfile.sv:866:49: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'csr_wdata' generates 64 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
866 | if (riscv::XLEN == 32) instret_d[63:32] = csr_wdata;
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:1362:46: Bit extraction of var[63:0] requires 6 bit index, not 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
1362 | privilege_violation = ~mcounteren_q[csr_addr_i[4:0]];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:1364:46: Bit extraction of var[63:0] requires 6 bit index, not 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
1364 | privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]];
| ^
%Warning-WIDTHEXPAND: /home/sirisli/cva6/core/csr_regfile.sv:1364:79: Bit extraction of var[63:0] requires 6 bit index, not 5 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.csr_regfile_i'
1364 | privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]];
| ^
%Warning-WIDTHTRUNC: /home/sirisli/cva6/core/frontend/frontend.sv:200:34: Logical operator LOGAND expects 1 bit on the LHS, but LHS's SEL generates 32 bits.
: ... note: In instance 'ariane_testharness.i_ariane.i_cva6.i_frontend'
200 | if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin
| ^~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk3.unnamedblk4.idx_base' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk3.unnamedblk4.shift' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk3.unnamedblk4.new_index' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk6.unnamedblk7.en' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.replace_en' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk6.unnamedblk7.idx_base' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk6.unnamedblk7.shift' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_itlb.plru_replacement.unnamedblk6.unnamedblk7.new_index' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk3.unnamedblk4.idx_base' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk3.unnamedblk4.shift' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk3.unnamedblk4.new_index' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk6.unnamedblk7.en' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.replace_en' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk6.unnamedblk7.idx_base' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk6.unnamedblk7.shift' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~
%Warning-LATCH: /home/sirisli/cva6/core/mmu_sv39/tlb.sv:158:3: Latch inferred for signal 'ariane_testharness.i_ariane.i_cva6.ex_stage_i.lsu_i.gen_mmu_sv39.i_cva6_mmu.i_dtlb.plru_replacement.unnamedblk6.unnamedblk7.new_index' (not all control paths of combinational always assign a value)
: ... Suggest use of always_latch for intentional latches
158 | always_comb begin : plru_replacement
| ^~~~~~~~~~~