[BUG] Inhibition of cycle counter
Created by: Tiago-R
Is there an existing CVA6 bug for this?
-
I have searched the existing bug issues
Bug Description
Hello! I found that the current implementation of the performance counter inhibition for the cycle counter does not actually inhibit the mcycle CSR increment every cycle but simple writes to it the value of the instruction retired count.
There might be a reason for this behavior to be desirable but it does not seem to follow the RISC-V specification.