CVA6 CSR spike discrepancies list

Created by: spidugu444

HI,

Please find the below list of CSRs which has discrepancies between CVA6 and spike

 

 

Sl no	Name	Address Offset	Width	Access Type	Reset Value	Display Name	STATUS	COMMENT
1	sstatus	0x100	32	RW	0x00000000	Supervisor Status	Spike Dependency	Need to disable FS field on spike end
2	mstatus	0x300	32	RW	0x00000000	Machine Status	Spike Dependency	Need to disable FS field and enable ube bit on spike end
3	misa	0x301	32	RW	0x4014_1105	Machine ISA	Spike Dependency	On MISA Bits 0, 2, and 12 behave like RW rather than WARL on spike end.
4	pmpcfg[0..1]	0x3A0	32	RW	0x00000000	Physical Memory Protection Config 0	spike dependency	Issue with default value reading as 0x01f
5	pmpaddr[7]	0x3B0 [+ i*0x1]	32	RW	0x00000000	Physical Memory Protection Address	spike dependency	Issue with spike configuration and default values
6	mvendorid	0xF11	32	RO	0x00000602	Machine Vendor ID	spike dependency	Need to configure reset value as 0x602 on spike end
7	marchid	0xF12	32	RO	0x00000003	Machine Architecture ID	spike dependency	Need to configure reset value as 0x01 on  spike end
8	icache	0x7C0	32	RW	0x00000001	Instruction Cache	spike dependency	Need to configure Custom CSRs on spike end
9	dcache	0x7C1	32	RW	0x00000001	Data Cache	spike dependency	Need to configure Custom CSRs on spike end

For MCOUNTEREN and SCOUNTEREN CSRs, even though when we write non-zero values these CSRs are always reading zero on spike end. The reserved field bit 12 for MIE and MIDELEG CSRs is reading one on the spike end when written with a non-zero value which it should be always zero.

Thanks