[BUG] About four-byte alignment on target addresses of control transfer instructions (branch_unit.sv)

Created by: yaohsiaopid

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Hi,

In core/branch_unit.sv the branch_exception_o.valid is raised high only if the branch/jump target address is not aligned on a two-byte boundary (line 94 checks only the LSB). That is, it enforces only two-byte boundary check, and does not raise exception when target address of JAL/JALR is not four-byte aligned. However, in RISC-V 2.1 specification p.16 says "The JAL and JALR instructions can generate a misaligned instruction fetch exception if the target address is not aligned to a four-byte boundary."

If my understanding is correct, I think the fix may need to change the condition of line 94 from. if (branch_valid_i && target_address[0] != 1'b0) branch_exception_o.valid = 1'b1; to
if (branch_valid_i && (target_address[1:0] != 2'b00)) branch_exception_o.valid = 1'b1;

Thanks!