minstreth CSR is failing while verifying access modes

Created by: spidugu444

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

As per riscv priviliged specification minstreth CSR return bits 63–32 of machine instructions retired counter.

While trying to verify access modes for minstreth CSR test is failing on verilator end as it is always reading Zero. whereas on spike end test is reading expected values and test is passing. For reference please find attached spike and verilator log files

riscv_spike_minstreth_csr_test_0.log riscv_verilator_minstreth_csr_test_0.log