Incorrect documentation of MIE, MIP, SIP, SIE and STVEC CSR'S in CV32A6_CSR manual
Created by: spidugu444
Is there an existing CVA6 bug for this?
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I have searched the existing bug issues
Bug Description
STVEC: This issue points out the STVEC documentation. In CV32A6_CSR documentation, Mode field access for stvec is mentioned as RW as shown below.
| Bits | Name | Display Name | Access Type | Reset |
|---|---|---|---|---|
| [31:2] | BASE | RW | 0b0 | |
| [1:0] | MODE | RW | 0b0 |
| Bits | Mode | Description |
|---|---|---|
| 1 | RO | MODE[1]: always 0 |
| 0 | RW | MODE[0]: 0 = direct mode, 1 = vectored mode. |