Incorrect documentation of mtvec CSR in user manual
Created by: spidugu444
Is there an existing CVA6 bug for this?
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I have searched the existing bug issues
Bug Description
This issue points out mtvec documentation. In CVA6 CSR documentation, Mode field access for mtvec is mentioned as RW as shown below.
| Bits | Name | Display Name | Access Type | Reset |
|---|---|---|---|---|
| [31:2] | BASE | RW | 0b0 | |
| [1:0] | MODE | RW | 0b0 |
As per the CVA6 for mtvec CSR mode field we have two implementation options i.e Direct Mode(00) and vector Mode (01).so the mode[1] bit is fixed to 0 making this bit to RO.
| Bits | Mode | Description |
|---|---|---|
| 1 | RO | MODE[1]: always 0 |
| 0 | RW | MODE[0]: 0 = direct mode, 1 = vectored mode. |