Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma

Created by: silabs-hfegran

Zero PMA regions,attribution mismatch between cv32e40x_mpu_sva and cv32e40x_pma

Given 0 PMA regions, PMA code still takes trans_debug_region_i into account, while mpu assertions do not. Occurred during simulation, and confirmed by code inspection - causes mismatches with atomic bit as that bit is enabled in the default configuration, and disallowed within the debug region:

cv32e40x_pma.sv:

    if(PMA_NUM_REGIONS == 0) begin: no_pma

      always_comb begin
        // PMA is deconfigured, use NO_PMA_R_DEFAULT as default.
        pma_cfg = NO_PMA_R_DEFAULT;

        // Debug mode transactions within the Debug Module region use PMA_DBG as attributes for the DM range
        if (trans_debug_region_i) begin
          pma_cfg = PMA_DBG;
        end
      end

    end

cv32e40x_mpu_sva.sv:

  always_comb begin
    pma_expected_cfg = NO_PMA_R_DEFAULT;
    if (PMA_NUM_REGIONS) begin
      pma_expected_cfg = is_pma_dbg_matched ? '{main    : 1'b1, default : '0} :
                         is_pma_matched     ? PMA_CFG[pma_lowest_match]       : PMA_R_DEFAULT;

    end
  end

Steps to Reproduce

Please provide:

core git hash: 8f4eb4cc
Command line: make comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt_debug CFG=clic_default USE_ISS=YES COV=YES RUN_INDEX=483 GEN_START_INDEX=483 RNDSEED=-585695672 WAVES=1 Note that the above state of core-v-verif is missing the appropriate debug region settings; the following two lines of code must be added inside the last else clause in the file after the line containing const string pma_cfg_name = "pma_noregion":

   parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000;
   parameter logic [31:0] CORE_PARAM_DM_REGION_END   = 32'h1A11_1000;

These will be added by an upcoming PR to core-v-verif