RTL packed/unpacked warning

Created by: Nicolas-Gaudin

RTL packed/unpacked warning

I got a packed/unpacked warning on an array declaration in debug_helper component when I compile the core with verilator under a core-v-verif environnement.

Component

https://github.com/openhwgroup/cv32e40x/blob/d25e3b5042c4d993271149c0cce5d12a88861018/bhv/cv32e40x_dbg_helper.sv#L45

rf_addr_t type is declared here : https://github.com/openhwgroup/cv32e40x/blob/d25e3b5042c4d993271149c0cce5d12a88861018/rtl/include/cv32e40x_pkg.sv#L609

Steps to Reproduce

//Having already Verilator and the riscv TC

git clone https://github.com/openhwgroup/core-v-verif cd core-v-verif git checkout cv32e40x/dev cd cv32e40x/sim/core #% set environment variables #% CV_SW_TOOLCHAIN = /opt/riscv #% CV_SW_PREFIX = riscv32-unknown-elf- make #% make command will compile the core using verilator and then simulate the core with a 'hello-world' code

Result:

%Warning-UNPACKED: /opt/core-v-verif/core-v-cores/cv32e40x/rtl/../bhv/cv32e40x_dbg_helper.sv:45:26: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked)
   45 |     rf_addr_t    rf_raddr[REGFILE_NUM_READ_PORTS];
      |                          ^
                   /opt/core-v-verif/core-v-cores/cv32e40x/rtl/../bhv/cv32e40x_core_log.sv:67:1: ... note: In file included from cv32e40x_core_log.sv
                   /opt/core-v-verif/core-v-cores/cv32e40x/rtl/../bhv/cv32e40x_wrapper.sv:39:1: ... note: In file included from cv32e40x_wrapper.sv
                   ... For warning description see https://verilator.org/warn/UNPACKED?v=4.216
                   ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.