Alignment requirement for atomic operations not checked

Created by: Silabs-ArjanB

The following two parts of the RISC-V spec have not yet been implemented:

For LR and SC, the A extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.

For AMOs, the A extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.

LSU needs to be fixed for this and rvfi_trap[13:12] needs to be extended for this. Assertion should be added that atomic transactions are never getting split and that on the data OBI output atomic transactions are naturally aligned.