debug CSR access in M-mode does not take exception

Created by: strichmo

Steps to Reproduce

Use this forked repo: https://github.com/strichmo/core-v-verif.git
5459b37d5ac846fa9171ff4334cd219af4c810c6
Run the generic_exception_test test with any seed

% makeuvmt test TEST=generic_exception_test

The test should fail with an assertion that fires when accessing dcsr in M-mode.

        ##0 cov_assert_if.illegal_insn_i;
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xmsim: *E,ASRTST (/work/strichmo/ip_rad_riscv/mdx/modules/core-v-verif/cv32e40x/tb/uvmt/uvmt_cv32e40x_debug_assert.sv,334): (time 15148800 PS) Assertion uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.u_debug_assert.a_debug_regs_mmode has failed (2 cycles, starting 15142800 PS)
UVM_ERROR @ 15148.800 ns : uvmt_cv32e40x_debug_assert.sv(336) reporter [CV32E40X_DEBUG_ASSERT] Accessing debug regs in M-mode did not result in illegal instruction