cannot determine condition on RVFI with debug external request and interrupt

Created by: strichmo

Component

Component:RTL: For issues in the RTL (e.g. for files in the rtl directory)

Steps to Reproduce

1. Use the strichmo fork: https://github.com/strichmo/core-v-verif.git
2. Use this branch: strichmo/pr/common_mk_fw_rule_cleanup
3. Use this bash (Should be head of branch): 2fa98e975aba2fae9660d9d93c3ff23b4c0f2ddd
4. makeuvmt comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt_debug SEED=1638053781

The instruction retirement at 9451.8 is a debug handler entry due to debug entry request. However an interrupt is also acknowledge (30) at this instruction retirement. Therefore the core will save the entry of the next interrupt (0x6954) in DPC. The current RVFI monitor considers interrupts and debug request in a mutually exclusive manner. Therefore the RVVI/ISS never sees the interrupts and CSRs start mismatching.

Attempted fix

I added code to the RVFI monitor (in UVM) to allow an interrupt request and debug request in the same cycle. These are signaled to the RVVI in order of interrupt request, debug request, instruction retirement. This fixes the current condition above.

However when running this fix across other tests, I see the same conditions on RVFI for debug entries where there has not been an interrupt request.

The RVFI signals are (rvfi_valid == 1, rvfi_intr == 1, rvfi_dbg_mode == 0, rvfi_dbg == 3, mcause[31] = 0x1). Because mcause may be left over from a previous interrupt, the above combination of signals is not a guarantee that we are seeing an interrupt + debug "instruction". It appears that we need another signal to truly communicate that an interrupt handler was "taken" by the core (even if the actual PC jump is deferred by debug request).