MPRV not cleared when core changes from debug to user mode.

Created by: silabs-anvesten

Component

Component:RTL

Comment: mstatus.MPRV bit should be cleared when exiting debug mode into user mode, this is not the case. Simulation must also be run without ISS as there is currently a mismatch error when writing changes to the dcsr.prv bit.

Steps to Reproduce

git hash: c8ed2efc63ad8f31cf90603f19fcd35c1dd45247 git branch to look into: https://github.com/silabs-anvesten/core-v-verif/tree/DebugBug make command: make test TEST=debug_priv_test CFG=pmp USE_ISS=NO