HWLoop count not updated when last instruction is a CSR access with pipeline flush

Created by: pascalgouedo

Issue description

When the last instruction of an Hardware Loop is a CSR access (MSTATUS, MEPC, MTVEC, MCAUSE, any counter) leading to a pipeline flush, lpcount is not decremented.

Component

Component:RTL: For issues in the RTL (e.g. for files in the rtl directory)

Steps to Reproduce

1. cv32e40p git tag cv32e40p_v1.7.0
2. core-v-verif git hash 6d973dda74bb666697f93d8ba0ba6131933ca4ad
3. command with ISS: makeuvmt test TEST=pulp_hardware_loop CFG=pulp_fpu USE_ISS=1 # Info (IDV) Instruction executed prior to mismatch '0x404(startZ_7+10): 30002373 csrr x6,mstatus' # Error (IDV) CSR register value mismatch (HartId:0, PC:0x00000404 startZ_7+10): # Error (IDV) Mismatch 0> CSR cc2 (lpcount0) # Error (IDV) . dut:0x0000000a (not updated) # Error (IDV) . ref:0x00000009 # UVM_ERROR @ 35034.300 ns : idvPkg.sv(55) reporter [] uvmt_cv32e40p_tb.imperas_dv.trace2api.state_compare @ 35034.000 ns: MISMATCH
4. command without ISS: makeuvmt test TEST=pulp_hardware_loop CFG=pulp_fpu USE_ISS=0 Never ending as inner loop lpcount is never decremented.