For pulp hwloops with hwloop count programmed to 0, count decrements at the end of loop to set lpcount to 0xFFFF_FFFF

Created by: dd-vaibhavjain

Issue Description

When HWLOOP count CSR lpcount0 is configured to 0, the loop count decrement after the last instruction of the loop sets the lpcount to 0xFFFF_FFFF.
In case of non-zero loop count, at the time of the last loop iteration the count is 1 and this final decrement sets it to 0.
But in the failing case the check for count > 0 is not done and decrements happens on already set 0 loop count value, causing the loop count to set to 0xFFFF_FFFF.
Refrence model does not do this decrement thus creating the mismatch.

Failing Test example using cv.setup instruction. By x29 reg (val = 0x0) From the test trace log: 00000e00 004ec72b cv.setup 0, x29, 0x4 x29:00000000

Test Log:

Info (IDV) Instruction executed prior to mismatch '0xe0c(hwloop0_nested_start_stream1+8): a1eb1453 flt.s x8,f22,f30'
Error (IDV) CSR register value mismatch (HartId:0, PC:0x00000e0c hwloop0_nested_start_stream1+8):
Info (IDV) 0> CSR cc2 (lpcount0)
Info (IDV) . dut:0xffffffff
Info (IDV) . ref:0x00000000
UVM_ERROR @ 9981.300 ns : idvPkg.sv(92) reporter [] uvmt_cv32e40p_tb.imperas_dv.trace2api.state_compare @ 9981.000 ns: MISMATCH

Dump Reference State GPR
0: 00000000 1: 00000002 2: 5efa8000 3: 80000000
4: 085755d7 5: e76c1614 6: 80000000 7: 8001e9c4
8: 00000000 9: 00000017 10: f18134cf 11: a10ffff6
12: 5efa82b0 13: f18134cf 14: 0000000a 15: 80000000
16: 00000000 17: 00000e10 18: 00022844 19: f18134c3
20: 13433f80 21: ffffffff 22: 00000e04 23: 00000000
24: 00000006 25: 00000df0 26: 00019ba4 27: 00000e20
28: 0001e9c4 29: 00000000 30: 00000100 31: 07d8acf0

hpmcounterh31: 00000000 lpstart0: 00000e04 lpend0: 00000e10 lpcount0: 00000000
lpstart1: 00000df0 lpend1: 00000e20 lpcount1: 000003f1 uhartid: 00000000

lpcount0 decrements to 0xFFFF_FFFF in the cv32e40p RTL

cv32e40p/rtl/cv32e40p_controller.sv Line 819

Component

Component:RTL

Steps to Reproduce

1. cv32e40p branch/hash - dev -> c520546c

2. core-v-verif setup :

• git clone https://github.com/XavierAubert/core-v-verif.git
• cd core-v-verif
• git checkout cv32e40p/dev_dd
• Hash -> 117ad5b120922d48e63edc0a91a81ebbd6616b5b

3. Running test:

• cd cv32e40p/sim/uvmt/
• make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG=pulp_fpu TEST_CFG_FILE=floating_pt_instr_en,gen_rand_int USE_ISS=yes RUN_INDEX=1 GEN_START_INDEX=1 SEED=1 WAVES=1