data forward violation when custom xpulp instruction, cv.insertr followed by fp instructions

Created by: dd-baoshan

Simulation shows below Imperas error messages which related to bsetr xpulp instruction.

From tracer log, we can see that the data forward rule is violated whereby the fmul.s rd is not reflecting correctly on cv.insertr r2

It was proven in waves whereby we can see that cv.insertr write to register earlier than its preceded fmul instruction (blue marker indicate fmul reg_write to X10 happen after cv.insertr reg_write to X20 )

Further debug shows that the apu_stall signal is not asserted when cv.insertr has dependency on X10 (the read_reg_valid_i[1] deasserted during cv.insertr decoding stage).

cv.insertr has alu_op_b_mux_sel_o set to OP_B_MASK in decoder_i

but dependency check for op_b has no include OP_B_MASK as option thus de-assert the apu_read_reg_valid[1]

Component:RTL

Steps to Reproduce

Please provide:

cv32e40p git hash : https://github.com/openhwgroup/cv32e40p/commit/4d281cf231fa2b5b7f2b600dd8b399a248c1f279
Users need to checkout below core-v-verif to replicate the issue. The reproduce steps as followings git clone --branch cv32e40p/bsm-github_cv32e40p_Issue_0907 https://github.com/XavierAubert/core-v-verif.git sandbox cd sandbox/cv32e40p/sim/uvmt make gen_corev-dv TEST=corev_rand_fp_instr_data_fwd_test CFG=pulp_fpu_zfinx_2cyclat SIMULATOR=vsim SEED=1406786435 TEST_CFG_FILE=floating_pt_zfinx_instr_en COREV=1 USE_ISS=YES make test TEST=corev_rand_fp_instr_data_fwd_test CFG=pulp_fpu_zfinx_2cyclat SIMULATOR=vsim SEED=1406786435 TEST_CFG_FILE=floating_pt_zfinx_instr_en USE_ISS=YES