Custom Xpulp memory instructions update register file wrongly | Simultaneous port writes

Created by: salaheddinhetalani

Issue Description

If preceded by multicycle F instruction and rd2 is same as rd1, memory RI/I instructions updates the destination register to the address value by the ALU port one cycle later, and thus the loaded data on LSU port is ignored as the ALU port write has a higher priority.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fdiv.s x16, x23, x0, DYN -> cv.ror x1, x0, x4 -> cv.lh.ri x4, x26(x4!) -> jalr x1, x0, 0

The instruction cv.lh.ri is decoded at t##-2 and executed updating the integer register file at t##0 writing x4 by two ports simultaneously. The ALU port writes rs1+rs2 value that is 32'h2000 to x4. At the same time, the LSU port writes the loaded data from memory 32'h400 to x4. Due to the ALU having higher priority, x4 is updated wrongly. This is due to a delay of the ALU port write that is supposed to have happened earlier, but due to having multicycle previous FDIV.S instruction, it got delayed by one cycle. The load instruction accesses the memory at t##-1 setting the memory request. The request is granted at the same cycle and the response from memory is valid at t##0.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (1),
    .PULP_CLUSTER     (1),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: TBU Flist: cv32e40p_fpu_manifest.flist VCD: bug_33.vcd

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Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.4_1