Custom read-only CSRs are updated with no illegal instruction exception raised

Created by: salaheddinhetalani

Issue Description

No illegal instruction exception raised for CSR instructions updating read-only uhartid or privlv CSRs.

Component

Component:RTL

RISC-V Specification

Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

csrrci x2, privlv, 4

The instruction csrrci is decoded at t##0 and executed updating the integer register file at t##1 writing x2 with the read value of privlv that corresponds to machine privilege level with no illegal instruction exception being raised as machine CSRs are not updated to reflect that.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (1),
    .PULP_CLUSTER     (1),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: TBU Flist: cv32e40p_fpu_manifest.flist VCD: bug_29.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.4_1