Custom Xpulp memory instructions set extra memory access

Created by: salaheddinhetalani

Issue Description

Custom load or store I or RI instructions set extra memory access in case they are preceded by a multicycle F instruction.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fdiv.s x15, x6, x24, RDN -> cv.lw.i x11, -1058(x23!)

The instruction cv.lw.i is decoded at t##0 and executed updating the integer register file at t##1 writing x23 and at t##3 writing x11 after reading the loaded data from memory. The load instruction accesses the memory at t##1 setting the memory request. The request is granted at t##2 and the response from memory is valid at t##3. What is odd is seeing unexpected new memory access set again at t##3. Which is as well true for the additional write of x11 at t##5.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (1),
    .PULP_CLUSTER     (1),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: TBU Flist: cv32e40p_fpu_manifest.flist VCD: bug_27.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.3_1