Non-Zfinx (F only) instructions execute with no illegal instruction exception raised

Created by: salaheddinhetalani

Issue Description

Illegal instruction exception is not raised for executing FMV.W.X, FMV.X.W, FLW, FSW or the compressed versions of them, as these instructions shouldn't exist if Zfinx is set.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

32'h42002007

The flw instruction 32'h42002007 is decoded at t##0 and executed updating the integer register file at t##1 with no illegal instruction exception being raised, as the associated CSRs highlighted are not updated.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: https://github.com/openhwgroup/cv32e40p/commit/d0d1c25374e3770c4335568ef16e84404cedbdea Flist: cv32e40p_fpu_manifest.flist VCD: bug_5.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.3_1